The present invention covers a method for the formation of polycrystalline silicon layers, which are localized onto zones covered with silica of a silicon plate, and a particular application of this process to the manufacture of a self-aligned, non planar, MOS device.
In the present description, the term "non planar MOS" is used to represent a field effect device which includes in particular the types currently called V-MOS and U-MOS transistors. The abbreviation "MOS" consists of the initials of the words metal-oxide-semiconductor". "V-MOS" indicates a MOS with V-shaped slots and "U-MOS" one with U-shaped ones. These V-MOS and U-MOS transistors operate vertically or roughly vertically and may be used in particular for applications in which relatively high voltages are applied and relatively high currents flow.
Generally speaking, in semiconductor component manufacture techniques, and more especially in integrated circuit manufacture techniques, the greatest possible miniaturization of the various elements is sought. To obtain this miniaturization, use is currently made of so-called self-aligning methods, i.e. methods which avoid using successive masks and enable several successive operations to be carried with one initial mask, these operations aligning themselves automatically on the designs determined by the initial mask.